Modifications to LDG antenna tuner

 

Status indicators

Debugging is a nightmare if you don't have any feedback, so I use the existing LED interface for 4 leds (J3 header, pins 5,6,7 and 8) which will be visible from the panel. Plus, if I'm clever and have too much time on my hands, I could write some software (to fill the remaining bytes in the EEPROM) that displays nifty idle patterns. At the least, I'll program a "talking" and a "listening" light to debug the communications (so I can tell if the correct unit is getting the commands).

Unit addressing

I use the Cap Up/Dn and Inductor Up/Dn (Port D, bits 2-5) as a unit code. Each board will have the appropriate lines tied high or low to create a 4 bit unit number, which will be used by the software to select which board should respond to the command. Conveniently, these lines come to a header (J3, pins 1-4), and, have pull-ups on them, so all you have to do is ground the ones that you want to be "zero". Ground is available on pins 9,13, and 14 of the same header.

Revision: 3 August 2002 - I've changed my basic control philosophy, and want to be able to use these in a distributed (at the feed) fashion, so I'll use a star, rather than bus, control, so we don't need unit numbers. Instead, I'll install pushbuttons (or a connector for pushbuttons).

 

QRP Antenna Tuner Modifications:

1) Serial communications - I'm going to use the special bootloader mode. The HC11, on power up, configures Port D, bits 0 and 1 as a serial communications interface. It sends a BREAK out the TxD (bit 1), which is configured as a open-drain. It looks to see if RxD drops at the same time. If it does (i.e. they are tied together with a pull-up, as is done on the stock LDG board), then it jumps to the previously programmed EEPROM. However, if the HC11 receives a $FF character at either the E clock /16/16 or Eclock/13/16 (4800 bps with a 4 MHz crystal), it goes into the special bootloader mode, where it expects another 256 bytes to follow, containing new software.

The TxD lines, which are left in open drain mode, form a bus. The software will recognize the appropriate unit's address, and it will send the data out the line. (Obviously, a start bit has to be LOW for this to work). Since the output drivers in the other units are turned off, they don't interfere.

Revised 3 Aug 2002: Bus technique is history. Star mode eliminates the need for addressing. Still need to break the lines, because I need to talk to them, but now, if I want to revert to "factory mode" it's just a jumper.

2) Wake up from STOP - Since we want to use the "STOP" mode to reduce RFI (the processor clock is stopped in this mode), we need a way to wake the processor up. In the original LDG tuner, this was done using the "Tune" switch (TUNESW, J3-pin 10) which is tied to the XIRQ and IRQ lines of the 'HC11. We will drive this line with an open collector driver from the RTS line of the RS232 interface.

Revised 3 Aug 2002: Still nice to have the line separate from the tune switch

3) Reset - Just in case everything goes awry, it is nice to be able to reset the system without having to power cycle. This requires adding a line to the processor to pull down RESET*.

 

Hardware changes

Here are the specific hardware changes I made to the QRP antenna tuner board, as received from LDG Electronics. I cut the traces using a Dremel tool, but an X-Acto knife will also work.

1) Unsolder and replace the existing 4.5 MHz crystal with a 4.0 MHz one. I ordered mine from Mouser. They're about $0.30 each.

2) Cut the trace from the pull up to PD0 and PD1. The easiest place to get at this is on the top of the board, next to the SIP resistor array.

3) Cut the trace between PD0 and PD1. The trace runs from pin 20 under the socket on the top side to a via in the corner. Then, the trace runs from the via to pin 21 on the bottom side where it is accessible. Cut the trace between the via and the pad for pin 21.

4) Solder a wire to pin 21, TxD. (Grey wire)

5) Solder a wire to pin 20, RxD. (Brown wire)

6) Solder a wire to the via with the XIRQ* signal. The XIRQ line is used to wake up the 'HC11 from "STOP" mode, and is also connected to the "tune" switch line on the J3 header, pin 10. (Green wire)

7) Solder a wire to a via with the RESET* signal. This will be driven by an open collector driver from DTR on the RS232 interface, so that you can drop and raise DTR to reset the processors. (Orange wire)

8) Power connections at J4. (+12V: Red wire, Ground: Black Wire)

Future modifications

Increasing capacitance range (on the bottom end).

Preliminary calculations indicate that I need a bit more resolution on the capacitance on the antenna inputs, primarily for operating at higher frequencies (like 10m band), where you need pretty small C's. Since the capacitor will always be hooked on the antenna side (Any C necessary on the junction will come from the other tuner), we don't need to use the Hi/Lo Z relay. Instead, this relay is used to switch a series cap in or out of the arm of the L. The trace from the "transmitter" end (actually the antenna end in this application) to the NC relay contact is cut. A TBD pF capacitor is added between the two fixed contacts of the relay.

 



ldgmod.htm - revised 16 September 1999, Jim Lux
revised 4 August 2002
back to implementation details
back to Phased Arrays
radio home
Jim Lux home
email comments jimlux@earthlink.net