68HC11 OpCode Map

by

Tom Dickens


Since 1/20/2003 (page active since 7/28/2002)
Last updated:

I have maintained a 68HC11 Information web-site since 1997 as I work on personal and commercial 68HC11-based projects. One reference that I periodically want to use is an opcode map, which can also be used as a reverse-directory (given the opcode number, what instruction is it?). I have not been able to find a good one on the web, so I finally generated my own. I hope you find this as useful as I have...

I also have a good alphabetic listing of the 68HC11 instructions that includes cycle (timing) information and condition-code changes if you want to access the information from that direction.

Observations: Typical of opcode layouts, the 68HC11 opcodes are organized in an orderly manner, as can be readily seen in the tables below. For example, all of the branch-on-condition instructions are located in the "2" column on page 0, meaning if bit 5 (00100000 counting from right-to-left starting at zero) of the opcode is set, then the instruction is a Bnn-type. I can imagine the on-chip logic being implemented as a highly-effective bit-oriented sieve to quickly dive down into, and activate, the opcode-specific logic.

There are a total of 311 68HC11 opcodes. With an 8-bit number spanning 256 values, it is clear that to implement 311 opcodes requires a scheme using a "special" opcode to indicate that the real opcode is in a different table (called a page). This special opcode is called a "prebyte" since it is a special number which is seen before the actual page-N opcode. It is interesting to observe that for the 68HC11 opcode mapping, instead of implementing a single prebyte that specifies to find the opcode on a second page, it implements 3 different prebytes which take us to 3 different auxiliary pages. As implemented, the primary page (page 0) includes 233 valid opcodes plus 3 prebyte codes, resulting in 20 undefined opcodes. If the processor encounters one of these undefined opcodes while running (for example, the number $42 -- in hex notation of course) it will throw an Illegal OpCode exception. Page 1 below includes 64 valid opcodes, page 2 has 7, and page 3 only has 4 opcodes defined. I can only guess that the on-chip logic was much more efficient with this design as opposed at using a 2-page solution.

Notice that all of the instructions dealing with the Y register use the prebyte. Looking at the timing (number of cycles) to execute instructions (detailed here), we see that the Y-register instructions take an extra clock cycle compared to the same instruction using the X register. For example, the ABX instruction takes 3 cycles while the ABY instruction takes 4 cycles. This is one of the costs of climbing through the prebyte. The other cost is the number of bytes the instruction requires; the prebyte takes up an additional byte of program memory. For these reasons (program size and execution speed) the use of the Y register is typically kept to a minimum by 68HC11 programmers. But of course, use the Y register if you need it since a few bytes of program memory is well worth the price of having a second index-register available.


The following information is compiled from various Motorola documents, including much
from Section 3.6 of the M68HC11E Family Technical Data manual (M68HC11E.pdf).

The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in a single 8-bit binary number.

A 4-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. As its name implies, the additional byte precedes the opcode. A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. The operands contain information the CPU needs for executing the instruction. Complete instructions can be from one to five bytes long.

Six addressing modes can be used to access memory: Immediate, Direct, Extended, Indexed, Inherent, and Relative. All modes except inherent mode use an effective address in the operand, which are 1 or more bytes following the opcode. The effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed. The effective address can be specified within an instruction, or it can be calculated. Depending on the exact instruction, the operand for the particular addressing mode will be determined.


Address Modes:

The opcode table cells have been color-coded to indicate the addressing mode of the instruction as follows:
Addressing
Mode
Operand
(other bytes)
Description
INH -none- Inherent: In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. These are 1- or 2-byte instructions.
REL rr Relative: The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte instructions.
IMM ii
ii jj
Immediate: In the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. There are 2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction.
DIR dd
dd mm
dd mm rr
Direct: In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00$FF are thus accessed directly, using 2-byte instructions. Execution time is reduced by eliminating the additional memory access required for the high-order address byte. In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses.
EXT hh ll Extended: In the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required). One or two bytes are needed for the opcode and two for the effective address.
IND,X ff
ff mm
ff mm rr
Indexed: In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (IX or IY). The sum is the effective address. This addressing mode allows referencing any memory location in the 64-Kbyte address space. These are 2- to 5-byte instructions, depending on whether or not a prebyte is required.
IND,Y

The possible Operands are defined as:


Page 0, No Prebyte

Most Significant Digit -->> (example: the BRA opcode is $20 and STOP is $CF)
  INH INH REL INH INH INH IND,X EXT IMM DIR IND,X EXT IMM DIR IND,X EXT
       0 1 2 3 4 5 6 7 8 9 A B C D E F
0 TEST SBA BRA TSX NEGA NEGB NEG NEG SUBA SUBA SUBA SUBA SUBB SUBB SUBB SUBB
1 NOP CBA BRN INS         CMPA CMPA CMPA CMPA CMPB CMPB CMPB CMPB
2 IDIV BRSET BHI PULA         SBCA SBCA SBCA SBCA SBCB SBCB SBCB SBCB
3 FDIV BRCLR BLS PULB COMA COMB COM COM SUBD SUBD SUBD SUBD ADDD ADDD ADDD ADDD
4 LSRD BSET BCC DES LSRA LSRB LSR LSR ANDA ANDA ANDA ANDA ANDB ANDB ANDB ANDB
5 ASLD BCLR BCS TXS         BITA BITA BITA BITA BITB BITB BITB BITB
6 TAP TAB BNE PSHA RORA RORB ROR ROR LDAA LDAA LDAA LDAA LDAB LDAB LDAB LDAB
7 TPA TBA BEQ PSHB ASRA ASRB ASR ASR   STAA STAA STAA   STAB STAB STAB
8 INX PAGE1 BVC PULX ASLA ASLB ASL ASL EORA EORA EORA EORA EORB EORB EORB EORB
9 DEX DAA BVS RTS ROLA ROLB ROL ROL ADCA ADCA ADCA ADCA ADCB ADCB ADCB ADCB
A CLV PAGE2 BPL ABX DECA DECB DEC DEC ORAA ORAA ORAA ORAA ORAB ORAB ORAB ORAB
B SEV ABA BMI RTI         ADDA ADDA ADDA ADDA ADDB ADDB ADDB ADDB
C CLC BSET BGE PSHX INCA INCB INC INC CPX CPX CPX CPX LDD LDD LDD LDD
D SEC BCLR BLT MUL TSTA TSTB TST TST BSR JSR JSR JSR PAGE3 STD STD STD
E CLI BRSET BGT WAI     JMP JMP LDS LDS LDS LDS LDX LDX LDX LDX
F SEI BRCLR BLE SWI CLRA CLRB CLR CLR XGDX STS STS STS STOP STX STX STX

Notes: The following mnemonic pairs generate the same opcodes. Conceptually they are different, but logically they are identical (use the proper one in your code to make your code clearer and easier to understand). Only the first one of each pair is listed in the tables: ASL/LSL, ASLA/LSLA, ASLB/LSLB, ASLD/LSLD, BCC/BHS, BCS/BLO.


Page 1, Prebyte of $18

Most Significant Digit -->> (example: the TSY opcode is $30)
  INH IND,Y           INH                     IND,Y           IMM DIR IND,Y EXT IMM DIR IND,Y EXT
       0 1 2 3 4 5 6 7 8 9 A B C D E F
0       TSY     NEG       SUBA       SUBB  
1                     CMPA       CMPB  
2                     SBCA       SBCB  
3             COM       SUBD       ADDD  
4             LSR       ANDA       ANDB  
5       TYS             BITA       BITB  
6             ROR       LDAA       LDAB  
7             ASR       STAA       STAB  
8 INY     PULY     ASL       EORA       EORB  
9 DEY           ROL       ADCA       ADCB  
A       ABY     DEC       ORAA       ORAB  
B                     ADDA       ADDB  
C   BSET   PSHY     INC   CPY CPY CPY CPY     LDD  
D   BCLR         TST       JSR       STD  
E   BRSET         JMP       LDS   LDY LDY LDY LDY
F   BRCLR         CLR   XGDY   STS     STY STY STY


Page 2, Prebyte of $1A

Most Significant Digit -->> (example: the CPY opcode is $AC)
                                                                                  IMM DIR IND,X EXT IMM DIR IND,X EXT
       0 1 2 3 4 5 6 7 8 9 A B C D E F
0                                
1                                
2                                
3                 CPD CPD CPD CPD        
4                                
5                                
6                                
7                                
8                                
9                                
A                                
B                                
C                     CPY          
D                                
E                             LDY  
F                             STY  


Page 3, Prebyte of $CD

Most Significant Digit -->> (example: the CPX opcode is $AC)
                                                                                                      IND,Y                               IND,Y          
       0 1 2 3 4 5 6 7 8 9 A B C D E F
0                                
1                                
2                                
3                     CPD          
4                                
5                                
6                                
7                                
8                                
9                                
A                                
B                                
C                     CPX          
D                                
E                             LDX  
F                             STX