U.S. Patent granted on Oct. 25, 1977
Authored by Robert C. Abraham and James E. D. Cline, and assigned to Pertec Computer Corporation
This document by inventor James Edward David Cline SSN# 525-82-1047
A phase-locked loop is provided with a phase detector capable of providing phase error magnitude and direction information for synchronizing a voltage controlled oscillator with a train of data pulses spaced apart in integral multiples of a fundamental clock period using an edge-triggered flip-flop and simple digital logic gates.
SCHEMATIC shows the data pulse train positive pulses releasing the D-flip-flop from being cleared, and opening a pair of two-input NAND gates. The D-input is held high. The flip-flop's clock input rising edge triggers the D-flip-flop, which has its Q and Q-bar outputs being the other inputs to the two NAND gates. Those gates differentially drive a low pass filter, whose output controls the frequency of a voltage controlled oscillator, which in turn provides the previously mentioned rising-edge clock signal for the D-flip-flop.
The rising edge of the VCO oscillator's output splits each data pulse into two, and if the two split parts are not equal in width, then the difference shifts the frequency of the VCO so as to make the two halves equal. Since the feedback signal is produced only when a data pulse arrives, the discontinuous nature of a data pulse train does not prevent phase lock on its fundamental implicit clock frequency.
Robert C. Abraham, Thousand Oaks;
James E. D. Cline, Northridge;
both of Calif.
Pertec Computer Corporation.
APPL NO: 695,323
Filed: June 14, 1976
Lindenberg, Freilich, Wasserman, Rosen and Fernandez
USAGE: This circuit was in Pertec's first MFM read-write disk drive systems, and mainly used in its non-removable hard disk drives. Later, MFM was standardized in a somewhat different format, requiring a different type of phase lock loop synchronizer.
Copyright © 1995 James Edward David Cline
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