EE215B Final Project Report

 

Ground Bounce Minimization

 

 

 

 

 

 

 

 

 

 

 

 

Tom Hsieh

ID# 402952298

hsiet@earthlink.net

http://home.earthlink.net/~hsieht

Introduction

Ground bounce is inductive noise seen on the ground and power lines when the input of a circuit is switched.  Although ground bounce is only applicable to bonding wires in current VLSI design, its effects will be seen on-chip in the future because of voltage scaling (which causes a reduction in noise margin) and increasing clock frequency.  The goal is to characterize ground bounce through simulations and define a guideline to reduce the ground bounce effect.

Theory

An inductive model used to simulate ground bounce consists of two inductors coupled to the supply and ground lines and a capacitor coupled to an inductor and then to the output of the inverter.  This circuit is then cascaded in a chain (Figure 1). 

Figure 1 Model of N-output CMOS Buffers

When the PMOS opens, the inductor, PMOS resistance, and the output capacitor will form an RLC circuit.  Similarly, when the NMOS opens, the capacitor will discharge and form the same circuit with the ground inductor (Figure 2).  In a series RLC circuit, three cases can occur.

 

·        Under Damped, L>4R2C

·        Over Damped, L < 4R2C

·        Critically Damped, L=4R2C

 

The under damped case will cause a voltage drop on the supply and a voltage rise on the ground and then return to its original voltage.  The over damped case will cause ringing.  The critically damped case can never occur because resistance of the transistor is not constant. 

The following variables are defined for Figure 2. 

·        Rd = 1 / [2bn (Vgs-Vtn)]  where bn , Vgs, and Vtn are design parameters. Resistance is also assumed to be linear.

·        Rtot = Rd/N

·        Ctot = Cpad N

·        Ltot = Lpad / N  +  (Lpwr/M) (Lgnd/K) [2]

 

Simulations

            Simulations were done using an inverter coupled to an inductor on the supply and ground and a load capacitor CL (Figure 3).  The circuit model was simulated in HSpice using transistor models that were obtained from ftp://ftp.mosis.edu.  The transistor models are listed next.

 

·        Tech 1 – (1.2µm) n882-params.txt

·        Tech 2 – (0.5µm) n8BN-params.txt

·        Tech 3 – (0.25µm) N99y-params.txt

 


Figure 3 The simulation model used

A.                Switching Response

The switching response was simulated using the following values

 

·        L = 1nH

·        C = 10pF

·        W/L(p, n) = 40, 20

 

The result shows a rise in supply bounce as the switching speed is increased (Figure 4).

 

Figure 4 The amount of supply bounce increase with switching speed and technology

The simulation illustrates that building the fastest circuit is not always desirable as the technology increases.  When the switching speed of a circuit increases, it becomes more susceptible to noise and may become unreliable.  However, sometimes a designer will design a circuit with a strong current drive for the worse case scenario.  Since the worst care rarely occurs, the output current will always be higher than necessary.  For those particular cases, a current-controlled output is desired (Figure 5). 


 


Figure 5 A current-controlled output

 

The problem with the current-controlled inverter is the reduce voltage swing. 

 

B.                Decoupling Capacitor

Another way to reduce ground bounce is to add a decoupling capacitor between supply and ground (Figure 6).


 


Figure 6 Reducing ground bounce by adding a decoupling capacitor

 

If the inductance on the supply and ground line are the same, then the current on the supply line will flow to ground and cause the bounce to reduce by 50%.  Furthermore, the current are oscillating at the same phase and frequency.  Therefore, the noise margin remains constant.  The magnitude of the decoupling capacitor must be determined.  In the simulation, the ground bounce seemed to be minimized at 10pF using L=10nH, CL=10pF, and W/L (p,n) =40,20 (Figure 7).


Figure 7 Ground Bounce vs Decoupling Capacitor

 


A designer never wants to conservative and place a capacitor that is too large because die area is expensive.  However, under-designing will decrease the noise margin.  The coupling capacitance should be chose based on the following formula:

 

Cd=(Ip/Vp)2 L

 

where Ip is the peak current, Vp is the peak voltage, and L is the inductance.  A good rule of thumb is to choose Cd to be approximately 100 CL. 

C.                Capacitive Loading Effect

After simulating the inductance with the loading capacitance with W/L (p, n) = 40, 20, it was determined that changing the load capacitance has very minute effects on the ground bounce (Figure 8).


Figure 8 The effect of load capacitance

D.                Inductive Effects

Simulating the inductive effect is similar to showing the situation where wire length increases.  The ground bounce should also increase.  Using W/L (n,p) = 40,20 and CL= 10pF, the results show increasing noise with increase inductance.  Furthermore, smaller technologies become more susceptible to the noise (Figure 9).


Figure 9 Inductive effects for different technologies

 


Some methods to reduce wire inductance is to shorten the length, use material with smaller inductive effects, and connect wires in parallel.

 

E. Simultaneous Switching

Simultaneous switching occurs when a chain of circuit switch at the same time.  The effect of this is a large change in current resulting in a large ground bounce.  Simulating a chain of inverters is equivalent to simulating one inverter with the W/L ratio scaled up to the number of simultaneously switching circuits.  Using 10uF as the load capacitance, the voltage bounce increase as the chain of inverters where increased.  The amount of noise eventually saturates (Figure 10).


Figure 10 The amount of noise vs Simultaneous Switching

 


There are several methods to reduce simultaneous switching noise.  First, design and schedule the switching so the minimum number of circuits are switching at the same time.  For example, clock gating circuits should not shut down and open all the units simultaneous but rather one unit a time.  The cost is performance but the gain is reduced noise.   Finally, adding quiet lines to the circuit will also decrease the load the ground bounce (Figure 11).  The quiet lines are not switch, thus the output capacitor acts as a decoupling capacitor from supply to ground.

Conclusion

The methods of reducing ground bounce are summarized below.

 

·        Use dedicated power and ground planes.

·        Place 1 pair of dedicated power and ground planes for high ratio performance over cost.

·        Place chip capacitors close to the I/O pad in the electrical path.

·        Reduce length of electrical path (reduces inductance)

·        Place critical outputs away from switching output pads

·        Use minimum strength drivers with slew rate control

·        Reduce capacitance loading in switch lines

·        The capacitance on the quiet line acts as the de-coupling capacitor between ground and the supply.

·        Choose decoupling capacitor to be 100CL

 

Figure 11 Quiet Line Effect

References

[1] Pant, Mondira Deb, and Pant, Pankaj, and Wills, D. Scott “An Architectural Solution for the Inductive Noise Problem Due to Clock Gating” ACM 1-58113-133-X/99/00008 (1999): 255-7.

 

[2] Gabara, Thaddeus, “A Closed-Form Solution to the Damped RLC Circuit With Applications to CMOS Ground Bounce Estimation” IEEE 0-7803-3302-0/96 (1996): 73-78.

 

[3] Chen, Liren and Sen, Bidyut, “Measurement Study on Simultaneous Switching Noise” IEEE 0-7803-3034-X/95 (1995): 40-42

 

[4] Huang, C.C. and Loh, Bill, and Wong, Florence, “Ground Bounce Study of 304 Lead Interposer MQFP with On-Chip Decoupling Capacitor Test Die” 0-7803-2639-3: 343-348

[5] Rabaey, Jan M. Digital Integrated Circuits: A Design Perspective. Prentice Hall,Inc. 1996. Pg 391, 428-502.

 

[6] Heydari, Pedram and Pedram, Massoud, “Analysis and Optimization of Ground Bounce in Digital CMOS Circuits” 0-7695-0801-4/00