Clock gating is a method shutting off processor units that are not in use. This is an important scheme to use to minimize power consumption. However, as a demand for performance increases, higher clock frequencies and voltage scaling will become a problem. When frequency rises, the effects are larger ground bounce (also known as switching noise). With voltage minimization to save power, the noise margin of digital circuits continue to decrease. Synchronization problems will arise from these effects. Currently, there is a proposed method of reducing ground bounce by introducing wake and sleep time. However, the cost is degradation in performance. During the time that the resources are awakening, some execution time is lost [1].
Although the performance cost is minimal for the proposed method, the wake and sleep time must continue to increase when frequencies increase further. This will result in greater penalties in performance. However, if ground bounce can be minimized independent of the wake and sleep time, then the problem will be ameliorated. Therefore, the topic of interest is the reduction of ground bounce for clock gating. The research will be conducted in the following order.
i. Did I meet my expectations?
ii. Can the research be carried further?
iii. How can the research be improved?
I do not have a partner and was wondering if you can pair me up with someone who may have the same topic. I can be contacted at:
Email: hsieht@earthlink.net
References
[1] Pant, Mondira Deb, and Pant, Pankaj, and Wills, D. Scott “An Architectural Solution for the Inductive Noise Problem Due to Clock Gating” ACM 1-58113-133-X/99/00008 (1999): 255-7.