A 50fA Input Current Junction-Isolated JFET Opamp

JoAnn P. Close, Lewis W. Counts
Analog Devices
Wilmington, MA

Copyright © 1986 IEEE. Reprinted from International Solid-State Circuits Conference Digest of Technical Papers, Vol. 29, February 19-21, 1986, pp. 12-13, 284-285.

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OPERATIONAL AMPLIFIERS with input currents below 100fA, offsets below 1mV, and drifts below 10µV/°C, fabricated with discrete components and hybrid technology, will be reported. The monolithic amplifier, to be described, uses a low leakage four-terminal JFET employing a junction-isolated process to achieve typical input currents of 50fA. Circuit techniques and laser trim of on-chip thin film resistors have been developed to adjust offsets to under 1mV, and drifts to below 5µV/°C.

MOSFET and JFET input stages generally are used in monolithic low-input current amplifiers. MOSFET devices have extremely low leakage, but require over voltage protection diodes which can increase the input current to 1pA or more¹. The low frequency voltage resolution of MOSFET inputs is limited by high 1/f noise due to surface effects on the MOSFET channel. Previously reported ion-implanted JFETs have an N+ shield connected to the pocket N-epitaxy of the device to form a gate on each side of the P+ implanted channel, as depicted in Figure 1a. This buried channel reduces substantially the voltage noise compared to MOSFETs. However, a substantial leakage from the N backgate to the substrate and P isolation contributes to the JFET's input current. 2pA input current has been reported for amplifiers employing this input JFET². Dielectric isolation has been used to eliminate the backgate to substrate leakage, producing amplifiers with gate currents of 1pA³.

The low-leakage four-terminal JFET is depicted in Figure 1b. The P+ source diffusion completely surrounds the P+ drain diffusion and N+ frontgate contact.

The P channel and N shield implants terminate at the inner perimeter of the source diffusion. This forms a JFET with the frontgate electrically isolated from the N epi backgate. Frontgate leakage currents of 50fA have been achieved with 3.5 square mils of frontgate area, the minimum area possible for this process. Leakages from the backgate to the source, drain and substrate total 2pA for this device under normal operating conditions.

Since transconductance is almost equally divided between the two gates (60/40 in this case), the backgate should be referenced to a low-noise bias point to minimize total input noise. Punch through breakdown will occur when the potential between the two gates exceeds the JFET's pinchoff voltage causing large currents to flow between the two gates. For low-leakage operation the backgate should be kept within 100mV of the frontgate. If the frontgate is biased a Vbe more negative than the source, the backgate will inject minority carriers into the channel, resulting in NPN transistor action between the gates.

The circuit and layout have been designed for low input current, while maintaining low offset and drift. Figure 2 is a schematic of the amplifier. A pair of minimum sized four-terminal JFETs (J6 and J7) comprise the input stage. The input devices are cascoded by J8 and J9 to minimize further input leakage and to improve CMRR. Current mirror Q17, Q18, and Q19 is heavily degenerated to minimize its contribution to input offset and noise voltage. Offset voltage drift is trimmed using R5 and R6. R3 and R4 are trimmed to null offset voltage at 25°C.

The amplifier biasing was designed to keep the backgate within 100mV of the frontgate under static conditions, limit the current through the input JFETs' gates during large signal transients, and provide a low temperature coefficient current to facilitate accurate and stable offset and drift trimming. J1A, B are two four-terminal JFETs geometrically identical to the input devices. The back and front gates of J1A, B are connected, forcing an equal gate to source voltage (VGS1) for the backgate and frontgate junctions. R1 converts VGS1 to a current, which is mirrored 1:1 via Q1 to the input stage. R1 and R2 have equal values, so this current reproduces VGS1 across R2. Since J1A, B and J6 and J7 operate at identical current densities, their gate to source voltages will track; the potential at Q14's base and at the BG1 and BG2 nodes will equal the voltage at the amplifier's inputs within l0mV. Lateral PNP's Q8, Q9, Q13, Q14, and current sources made up of Q9, Q10, and Q11, Q12 limit the current through the input device's gates during large signal transients. To provide a low (±200ppm) temperature coefficient current to the input stage, R1 is trimmed such that J1A, B is operating at its zero TC drain current of 60µA. R2's value is then trimmed to equal R1's value.

Figure 3 is a photo of the amplifier chip. Input JFETs J6 and J7 and bias JFET J1A, B are centrally located to facilitate matching and to reduce mechanical stress effects. The input lines and pads in the upper left corner are guarded by lines connected to the BG1 and BG2 bias points.

Table 1 summarizes the performance of the amplifier. Offsets below 300µV and drifts under 5µV/°C have been achieved for trimmed and packaged devices. Figure 4 is a histogram of fine inverting input current distribution for 43 parts. Figure 5 is a photo of the amplifier's large signal response when used as a unity gain follower.

Footnotes

¹ Schade, O.H., Jr., "A New Generation of MOS/Bipolar Operational Amplifiers", RCA Review, Vol. 37, p. 404-424; Sept., 1976.

² Russel, R.W. and Culmer, D.D., "Ion Implanted JFET-Bipolar Monolithic Analog Circuits", ISSCC DIGEST OF TECHNICAL PAPERS, p. 140-141, 243; Feb., 1974.

³ Milliway, S., "Monolithic Op Amp Hits Trio of Lows", Electronic Design, p. 97-102; Feb. 9, 1984.

Acknowledgments

The authors wish to thank J. Lapham and A.P. Brokaw for development of the JFETs, P. Shephard for chip layout, G. Butler and D. Wilson for trim and test development, and D. Rulli for typing the manuscript.

FIGURE 1 (a) - Cross section of previously reported ion-implanted JFETs;
(b) cross section of low leakage four-terminal JFET.

FIGURE 2 - Schematic of current amplifier.

FIGURE 3 - Chip photo of current amplifier.

TABLE 1 - Performance summary of amplifiers.

FIGURE 4 - Inverting input current distribution.

FIGURE 5 - Amplifier follower response to 20V p-p square wave:
horizontal scale 2µS per division; vertical scale 5V per division.