While not as practical as other oscillator configuarations, this is a good example of the use of the phase-shifting properties of an RC network. To start the oscillation, inherent noise in circuits create a tiny signal at the transistor's base, a small portion of which is at our operating frequency. As the voltage and current on the base increases, the transistor's collector voltage drops and current increases, amplifying the signal--a voltage-signal inversion. The signal travels around the loop to the first of four RC stages (not dashed line around each stage--the transistor stage we break up even more in for our calculations). Each RC effectively delays the signal, with loss of amplitude, by 45° (60° each if you use three stages; two stages would require 90° each, which you could never quite achieve), creating a 180° phase shift functionally equivalent to another signal inversion. The transistor, seeing a voltage drop on the base again, reinforces the signal. Because there is no DC path in the signal loop, the signal voltage, reinforced as far as it can go, decays as capacitors charge, sending it in the other direction, thus oscillating. At 45°, the ratio of the lengths of the sides of the triangle (or our vectors, our phasors) are R=1, C=1, Z=SQRT(2).

Unloaded, the attenuation factor for the signal voltage through an RC stage is the ratio of the magnitudes of the resistance and impedence vectors, or
1 / SQRT(2) = 0.707, which would result in an attenuation of 1/4 after four stages of this. Since a rigorous solution is messy to calculate, we estimate. If we choose 2k or so for the R's, with an appropriate C that will have a similar reactance, we have 2k (capacitive reactance in source), plus 2k (resistance in source) in parallel with 4k (approximate load impedence). This would drag down the unloaded source voltage divider by roughly a third, or 0.707 * (2/3) = 0.5 approximate loaded RC attenuation, or an attenuation factor of 1/16 after four stages. Note that if we had used three RC stages, the attenuation is twice as much. This is how much gain the transistor must have at a minimum to compensate for the losses. Since we need less gain, the four-stage version is more stable, as well as allowing more range in the biasing resistances. Fortunately, the current gain for a healthy 2N2222 is over a 100 times. This is a good general gain value to use as a first-cut estimate with any small- and medium-power NPN transistor.

To design this circuit means to choose our component values since the configuration has already been determined. It is a common emitter, class A amplifier stage with three or four RC phase-shifting stages cascaded, forming a ring of interconnects back to the transistor base, having phase-shifted the collector signal a full 180°. Refer to the common-emitter transistor stage section of this text for more insight into its design. The trade-offs for the values are:

• Almost any NPN bipolar transistor with decent gain will work. The 2N2222 is one of the most commonly available.
• Supply voltage must be enough to turn the transistor on (0.7V) with overhead to work with (reduces your gains). Too high doth fry. 10V is good.
• Collector resistor must be low enough to provide drive for the first RC stage, but not too low for transistor power rating (100mW) or input needs.
• Collector resistor provides the voltage division for the output signal, but the current is set largely by the base pull-up, so choose relatively.
• Emitter resistor stabilizes a common emitter transistor circuit, but must not hog too much of the available output voltage.
• Base pull-up resistor both (1) sets voltage for the base to >0.7V with pull-down, thus establishing (2) the voltage on emitter resistor at 0.7V less.
• With the emitter resistor voltage being set by the base pull-up, the emitter, and thus the collector, current is established.
• Base pull-down resistor is both part of the last RC, and the lower half of the divider which sets the base voltage, and thence, the emitter at 0.7V less.
• Remember, when the transistor is on, the base-emitter voltage is always 0.7V for a silicon transistor and 0.3V for germanium.
• The loading effect of the base on the last RC stage is the emitter current divided by the current gain (ex: 5mA / 100 = 50µA)
• For efficient use of signal, the load should be 1-2 times smaller than the source.
• As a first cut, the collector and emitter resistors could both be the same as R, and a base bias pull-up resistor about 2R.
• Choose R to neither excessively load the collector nor waste it at the base through disuse.
• Frequency of oscillation f = 1 / (2 * pi * SQRT(6) * R * C)

Let's try determining a set of component values for this circuit. The resistor-transistor output can be modeled as three resistors in series. The maximum power is transferred to, and is being dissipated by, connected components whose impedences are equal to one another (the maximum power point), so imagine the three have equal resistances, and thus equal thirds of the supply voltage and dissipating equal amounts of power. (Another way to look at them is to consider they each have a significant part to play, so making them equal is a good start.) The output is at two-thirds of the supply voltage--the DC operating point from which our voltage swings--6.6±3V. The lower resistor we will also plan on having the same 3.3V across it. The lowest resistance we ought to use must not cause our components to exceed their 100mW ratings, so imagine we dissipate 33mW on each of the output components, just to give ourselves a 3-to-1 margin, or so. The resistors, then, would be:

P = E^2 / R ==> Rc = Re = E^2 / P = (3.3V)^2 / 0.033W = 300 ohms

The average (quiescent) current flowing in the output is then:

I = E / R = 10V / (300 * 3) = 10mA of collector current

So, we then have 0-20mA, full-swing.

I[b] = I[c] / current gain = 10mA / 100 = 100µA

Because the transistor b-e junction is like a diode, with a very nonlinear characteristic, very little voltage change will need to visibly take place--it is considered to be a current-driven device. The operating voltage on the base will be around 0.7V above that of the emitter. Since we've chosen 3.3V on the emitter:

V[b] = V[e] + 0.7V = 3.3 + 0.7 = 4.0V

Our base bias voltage divider should be "stiff" enough not to get jerked around excessively by the current demands of the base (200µA max), so we bias the base voltage divider to use several times that amount of current, say ten times or 2mA. The quiescent current through the bias divider on the base would be:

I[divider] = E[supply] / R[divider total] ==> R[div] = E[supply] / I[div] = 10V / 2mA = 5k ohms

Since we know the divider node is 4V, our pull-down resistance (also R) is:

I = E / R ==> R = E / I = 4V / 2mA = 2k ohms

Our pull-up resistance is then:

R[total] = R[pull-up] + R[pull-down] ==> R[p-u] = R[ttl] - R[p-d] = 5k - 2k = 3k ohms

We decide to choose our frequency to be 1kHz. We know R, then C must be:

f = 1 / (2 * pi * SQRT(6) * R * C) ==> C = 1 / (2 * pi * SQRT(6) * R * f) = 1 / (2 * pi * SQRT(6) * 2kohms * 1kHz) = 0.033µF

The emitter bypass capacitance is chosen to have low reactance at our oscillating frequency, say 1% of our emitter resistor. This allows any AC fluctuations on the emitter to be very near ground potential, as though the emitter resistor is shorted-out for AC but not DC:

X[C] = 1 / (2 * pi * f * C) ==> C = 1 / (2 * pi * f * X[C]) = 1 / (2 * pi * 1kHz * (300ohms * 0.01)) = 53µF

Let's model it in SPICE:

• Waveform slightly raggedy (but it works)
• 0-22mA (right about what we calculated)
• 3.3-9.8V (also what we expected)
• 3kHz (oops.)

Let's come up with an intuitive model for us technicians that's not so rigorous that we can both remember and at least partially analyze easily:

• (1) Measure actual frequency (SPICE is NOT reality, but this circuit is trivial): 2924kHz (3.42±.02e-4sec) or 4.28e-5 sec delay per RC section.
• (2) We know frequency is inversely proportional to both R and C from the original equation. The RC time constant is perfect for our needs.
• (3) 1 RC time constant = (2kohms)(032e-6µF) = 6.4e-5sec.
• (4) The ratio between the RC time constant and the empirical delay for one RC stage = 1.495.

Test the model:

• (5) Change all the schematic values at bit, randomly.
• (6) Calculate RC time constant =3kohms * .02e-6µF = 6e-5sec.
• (7) Value for actual delay of one stage would be 6e-5sec / 1.5 = 4e-5 sec.
• (8) Four stages (180°) of delay = 4e-5 * 4 = 1.6e-4 sec.
• (9) For a full cycle (360°) of delay = 1.6e-4 * 2 = 3.2e-4sec.
• (10) For 6 cycles = 1.92e-3.
• (11) Run simulation. SPICE empirically shows 1.91±.02e-3. So that seems to work.

This model would be a lot cooler if we could match it up to the phasors as the 1.50 fudge-factor is only good for a four-stage RC, but I really dislike fudge factors--they are hard to remember, prone to breakage, and a reminder that one is being lazy and not finding out what's up--but I would probably use this model to design such a circuit, since I find it of greater practical utility at this moment than the presumeably rigorous formula. As a technician, such an approach would likely work just fine. If the application was more rigorous, the engineer you worked for would doubtless scratch his head for a moment, smile, and proceed to sketch on his whiteboard just where that fudge-factor connected to the rigorous models, as much for his amusement as for your erudition.