A WIZARD'S ELECTRONICS COMPANION
While not as practical as other oscillator configuarations, this is a good example of the use of the phase-shifting properties of an RC network. It is a common emitter, class A amplifier stage with, typically, three or four RC phase-shifting stages cascaded, forming a ring of interconnects back to the transistor base. To start the oscillation, inherent noise in circuits create a tiny signal at the transistor's base, a small portion of which is at our operating frequency. As the voltage and current on the base increases, the transistor's collector voltage drops and current increases, amplifying the signal while inverting it (a 180° phase shift.) The signal travels around the loop to the first of four RC stages. Each RC effectively delays (or phase-shifts) the signal, but with a loss in amplitude. The goal is to provide another 180° phase shift from all our RC stages together so that we may provide positive feedback (a 360° phase shift) to the transistor stage. The transistor, seeing a voltage drop on the base yet again, reinforces the signal. Because there is no DC path in the signal loop, the signal voltage, reinforced as far as it can go, decays as capacitors charge, sending it in the other direction, thus oscillating.
|RC stages||Phase shift per stage|
=180 / Number of stages
|Min. gain req'd. *|
|2||90°||XC=Infinity * R||0||Infinite|
This circuit is excellent for analytical exercises because it incorporates transistor biasing and includes reactive components. It is simple enough that rigorous solutions have been calculated, such as the 3-stage phase shift oscillator *.
It should be noted that many such circuits are sensitive to biasing transistors carefully into their active regions. If a circuit is sensitive to transistor gain, component values and tolerances may result in an incorrect (or even non-working) circuit, even if rigorously calculated. Fairchild, for example, cites hfe (current gain) as 100-300 @ 150mA and 30 (min) @ 500mA. The data sheet may not make it clear what the correct biasing is for your chosen current. If you play around with the circuit with a modelling program, you will find the circuit has a functional window of only about +/-10% of RB (using no Re) in order to provide just the right amount of base current and voltage to be transformed by the transistor gain into a suitable collector DC operating point. To compensate for such built-in uncertainties, we improve the design by adding Re to reduce our dependency on the gain by a factor of several times. For frequency accuracy, tolerances on capacitors are often +/-10% or more; remember, too, that capacitors' frequency dependencies in materials and construction are not as good as resistors, and inductors are even worse.
It is useful for a fundamental understanding of circuit dynamics and rough calculations if it is broken into trivial subcircuits which can be analyzed to first-order. This provides an idiot-check on more rigorous analyses, and, if a functioning circuit is all you're after, often only needs a simple circuit tweak after construction. I'm outlining this one in painful detail in order to illustrate the general process because this circuit is deceptively simple. This circuit's oscillation frequency is particularly tricky because it is dependent on pretty much every component in it, so more rigourous solutions are recommended. Still, it is worth taking a walk through so we can understand these interdependencies. If you have the patience to follow this analysis, you will understand how and why every part of this circuit works and be able to apply these techniques widely.
Break circuit into simple subcircuits for analysis, four of which are simple RC networks and one a transistor amplifier (note dashed line around each stage). The circuit stages form a closed loop of attenuating RC stages which requires a minimum transistor stage gain to offset in order to achieve oscillation.
Select a transistor. Almost any NPN bipolar transistor with decent gain will work. The 2N2222 is one of the most commonly available for small-signal circuits, and has a current gain of at least a hundred for currents around 150mA.
Select power supply voltage. Supply voltage must be enough to turn the transistor on (0.7V) with overhead to work with (low voltage reduces your amplifier gains). Too high a voltage and we risk overheating components unnecessarily. Anything in the 5-15V range is the most common. For our example, we will use 10V.
Select your high-end power limits. This would be due to your collector-emitter current. Most discrete small-signal components are typically capable of dissipating 100-250mW. We will choose 50mW in the transistor. It is a good idea to allow a factor of two or more in power to reduce the chance of melting or burning if the power dissipation conditions are less than ideal. (You may also find yourself with an upper limit on your power supply current which will force you to go back and adjust your values. These trade-offs are the bread-and-butter of much of practical design work.)
Calculate power, voltage, and current in transistor output to stay within our power limits. Imagine a subcircuit which is just Rc, Re, and the transistor's collector-emitter side. The highest power dissipated in any one place is likely at the output of the transistor. Power transfer from our collector and emitter resistors (our "source") will be maximized when their sum is the same as that of the transistor (our "load"). (We are ignoring the loading effect of the first RC stage right now--remember, this is just to get a reasonable power dissipation.) The following relationships are reasonably true:
Since we know the transistor gets half the power, it is like giving it half the supply voltage for the same current
Calculate lowest Rc and Re based on maximum power allowed. Let's narrow our selection problem with Rc and Re. Having an emitter resistor stabilizes a common emitter transistor circuit, but must not hog too much of the available output voltage. Today, let us choose Rc = Re. This makes a very stable circuit, increasing the sensitivity to base bias from around +/-10% to about +/-50% and reducing our dependency on a specific transistor gain, but we have just limited our DC gain hFE to 1 (=Rc/Re). Later, we will steal back our lost gain in the AC domain with an emitter bypass capacitor.
Since we know current is 10mA, power for each is half of transistor's quiescent dissipation, and voltage dropped across each is half of Vce, we have more than enough information:
25mW is well within the 100mW of a typical 1% metal film resistor that is so common nowadays.
Adjust RC input impedence to take best advantage of available transistor signal output. Too low an impedence and voltage is dragged too low, too high and available power is thrown away. This circuit needs all the voltage it can get, so we'll allow throwing away some power to maximize signal voltage. At the least, we won't go lower than the 3dB point (equal impedences for maximum power transfer). So, we will keep the RC impedence > 250 ohms to guarantee modest attenuation. (Note most of the change in voltage across R will occur when XC is within a factor of several times that of R; many first order solutions then can be arrived at by assuming R = XC.) For this first-cut we will select R >= 250 ohms, which will make RC impedence roughly twice our lower limit. (There is some discussion concerning loading effects in the sections "Collector Capacitor Loading Effects" and "Emitter Capacitor Loading Effects" below.)
Select frequency of oscillation. For this example, we will choose 1kHz. In practice, circuit dynamics will cause frequency to be roughly twice as much. I describe the effect of the transistor stage on this in the next section after the first-order analysis. Since noise is being amplified and filtered, frequency lower limit is established by gain allowed by bypass capacitor value, and upper limit by phase shifts available in RC's and transistor. High frequencies will pass will negatively feed back through the base virtually unimpeded to ground, while very low frequencies won't find enough phase shift to reinforce themselves.
Select C for the RC's. Typically, capacitors come in much more limited values than resistors. There are series which only have two or three values per decade, and other series will generally include these values. The most common values in use, and which embody small size versus low noise, are the simple decade values of 0.1uF and 0.01uF. We will choose 0.1uF.
Calculate R to complement C at oscillation frequency. There is no trivial way to estimate the oscillation frequency better than within a factor of two or so short of using the derived equations. A 3-section RC uses f = 1 / (2 * pi * SQRT(6) * R * C), but we have a four section RC, so we use the following: *
1.33k ohms is comfortably above our 250 ohm lower limit while still not throwing away too much power.
Select DC operating point of transistor. When the transistor is off, all the voltage is across it, and when it is fully on, Vce is about 0.3V. So, the collector voltage (Ve + Vce) can swing from a low of 4.85 + 0.3V at saturation to a high of 10V when off. For maximum usage of this range, quiescent operating point of the collector should be:
The transistor amplifier stage must be biased into its active range, so some base current must be provided by Rb. The R of the final RC stage acts with it as a voltage divider, providing a reference voltage for the base of several times the needed base current. As Vbe approaches 0.7V, the transistor begins to turn on. Most of the voltage drop across Re will come from the collector current = Ib * Current Gain of the transistor, pulling the emitter voltage up to about 0.7V below that of the base where it begins to pinch off and reach a stable state. Thus, the emitter current is effectively controlled by Re and the base quiescent voltage.
First, we know we have 10mA quiescent current across 250 ohms for Rb. While a good first guess of current gain for an unknown transistor would be 100, if we use the classic 2N2222A NPN transistor, the hFE gain is typically rated 100 to 300 (precise gain would have to be measured directly.) A first-order estimate of base current required to control our quiescent emitter current (using hFE = 200) is
Base voltage divider current for a stiff reference voltage would be typically about 10 times base current:
With the emitter quiescent DC voltage needing to be 2.5V, the base quiescent voltage is 0.7V higher
The trouble is we already have the R of the final RC stage setting our base divider requirements with 1.33k ohms. This is over 20 times lower than we could get away with, but we go with it for now. We can ignore the load which is only about 1% of our source:
Estimate equivalent resistance through the base to ground. From the above calculations of quiescent base voltage and current, we have:
Calculate an emitter bypass capacitance which allows AC gain at our oscillating frequency to be high enough to sustain oscillation. The emitter bypass capacitor allows us to establish an AC operating point which is a bit different from the DC operating point of the transistor. Re creates a great deal of transistor gain degeneration (AC gain hfe here is Rc / XCe). If Ce is added in parallel with Re and is suitably large, the AC signal will find a low-reactance path on the emitter through the capacitor rather than the resistor and will return to us most of our lost gain (for our AC signal, not DC). If we want most of our gain back (say 100), we need a 100 times smaller reactance for the bypass capacitor than Re:
Estimate base reactance to the AC signal.
To really find the oscillating frequency and the required gain, we must calculate attenuation factors and phase shifts throughout this circuit. This is where a more rigorous solution is just as easy and certainly more accurate, since oscillating frequency is dependent on all four RC's, transistor gain, and the effect of the bypass capacitor. However, this section is included to try and demystify the operation of the transistor stage in this circuit, since it is relatively complex. Remember from our phasor diagrams that capacitor current leads the voltage by 90°, so each RC stage will shift the voltage signal effectively backwards somewhere between 0 and 90°, depending on frequency. Note this is just an artifact of the use of a repetitive signal; neither does not imply a perfect sinewave. The circuit is, after all, amplifying and filtering noise. A good example of this process is shown in the graph below. The red curve is the transistor collector, and the others show each RC stage "phase-shifting" the signal backwards while adding a bit of distortion (which varies a lot depending on circuit values).
The amplitude from each stage is the AC voltage division across the series capacitor and resistor minus the loading effects from the next stage. At 45°, for example, when the RC stage is unloaded, the portion of the AC input voltage across the capacitor is 0.707, and across the resistor is 0.707 (the unloaded attenuation factor for the RC stage--see phasor diagrams). This, in fact, would be the requirement (as shown in our first table) if we hadn't approached the circuit values more arbitrarily, throwing them off from optimal. Let's take a look at the results of several simulations and you'll see what I mean.
|Emitter Bypass Capacitor Cb|
|Xb (ohms; hfe=200)||154||1260||5920|
|RC1 (µs)||-45 (-34°)||-40 (-29°)||-16 (-33°)|
|RC2 (µs)||-45 (-34°)||-40 (-29°)||-16 (-33°)|
|RC3 (µs)||-45 (-34°)||-40 (-29°)||-16 (-33°)|
|RC4 (µs)||-100 (-75°)||-130 (-94°)||-16 (-33°)|
|Xb-e (µs)||+95 (+71°)||+90 (+65°)||+7 (+14°)|
|Xe-c (µs)||-105 (-79°)||-90 (-65°)||-30 (-62°)|
|Ø sum (µs; s/b 180°)||-245 (-185°)||-250 (-181°)||-87 (-180°)|
|Period (µs; |Ø * 2|)||480||500||174|
|Frequency (kHz; 1/Period)||2.1||2.0||5.4|
The degrees phase shift measurements are referenced to the actual oscillation frequency. That we are not seeing 45° on the RC's is due to the loading effect on RC4 and through the transistor stage which can be significant. The simulation numbers for base-to-emitter and emitter-to-collector phase shift are a bit crude in the table, so let's digress for a while and do a few purpose-built simulations to characterize transistor phase shifting with capacitive loads. We'll use Vcc=10V and Vb=0.1VAC pk-pk
|Transistor Phase Shifting with Capacitive Loads|
Note the AC voltage drop across the emitter bypass capacitor is quite small (Ve column). This reflects the small value of the input voltage. It is easy to get confused by the relatively large DC voltage--the collector DC current can directly contribute to the DC voltage on the emitter, but cannot perform the same service for the AC signal. Consequently, the AC voltage on the emitter will never be higher than that of the input in this circuit. However, it does contribute indirectly, as we shall see.
Now we can see from the table how the components affect phase shifts in the transistor. Base-to-emitter delays signal as we would expect since it is essentially a resistance in series with a capacitor to ground. The effect it has on our transfer characteristic is a little bit like magic, though. The dynamic emitter-collector resistance is dependent upon Vb-e at each instant (no surprises there). But, if you subtract the instantaneous DC voltage on the emitter from that of the base (not in table) you will get a sine wave signal which appears shifted backwards in time by the same number of degrees which you see the AC signal shifted from emitter to collector (dØe-c column in table). Why is this? Because in an RC circuit the voltage on the capacitor is delayed from that of the input as it charges through the resistance. The input rises to maximum while the capacitor voltage is still relatively low. By the time the capacitor begins to catch up, the input voltage is dropping again while still pulling up the voltage on the capacitor, making the difference between the two voltages peak earlier than that of the input. Since this differential voltage is our Vb-e control voltage as it charges and discharges Ce, our emitter-to-collector dynamic resistance is changing with the same negative phase shift. The collector, then, with the help of the collector pull-up resistor Rc, makes a simple voltage divider which creates a signal that sees this same negative phase shift for that frequency (with a signal inversion). If we are simply looking at AC signals without their DC components, this negative phase shift occurs invisibly and we simply see a negative phase shift from the emitter to the collector combined with the inversion of the signal.
Most of the interesting things happen when components are in their active regions and not jammed to some limit or other. We know Ce could be large, but that is costlier than small in the electrolytic capacitor world. We might imagine, then, that the lower limit would be where the gain noticeably declines and likely happens where the phase shift is around 45° (half of 90°). This turns out to be a nice enough assumption, but proving it takes you back to our interdependent stages problem and the fact we don't know our real oscillation frequency precisely. From the table, though, we could judge the minimum Ce to be around 6.4µF to give us our 45°. Note most of Ce charging current comes from the collector and Rc even though the control is still from the base--a simple check of the time constant of the principal values gives us a rough approximation of the period of our oscillation frequency:
Remember, too, this affects the AC gain. If we discount the parallel Re, and assume 1kHz for our oscillation frequency, our gain is:
In practice the oscillation frequency is roughly twice our chosen 1kHz because of our poor modelling estimates, so the gain is really closer to 20, which is close to what the circuit will balance itself at.
Since our RC's are shifting the signal effectively backwards, we might figure we either don't want too large an emitter bypass capacitance or we do want the base-emitter delay to counterbalance that of the collector. To sum up, the emitter bypass not only creates a positive phase shift to the emitter, but also a negative phase shift to the collector.
So, we just have to calculate the effect of Ce, right? Well, no. Further complicating this mess is the fact that a pretty broad range of reactive loads on the collector may not affect the positive phase shift value, but it does affect the negative one. We know that a capacitor to ground has a delaying action as it charges through the surrounding resistances. We should think, then, that this delayed signal on the collector (positive phase shift) amounts to a delayed charging voltage which tries to offset the negative phase shift created in the transistor with the help of Ce. In fact, that is what can be seen in the table. Studying the table, we see that dØe-c is pretty stable for the first three Ce of each set of four, showing a distinct shift whenever Cc is changed for each set. With nearly 90° with Cc = 0.01µF it can be assumed this is an insignificant load, and with nearly 0° with Cc = 10µF it is clearly far too much load on the collector. The hfe gains reflect this as they drop by a factor of about 15 times. We probably wouldn't want Cc much larger than 1µF (which would be the C in the RC's)--and indeed it turns out XCc = 159 ohms at 1kHz for 1µF, which just happens to be in the general area of Rc and the output impedence of the transistor stage. If we work back the other way, using 249 ohms as the output impedence of the transistor stage (it's a bit more complicated than that, but remember this is a first-order approximation, so it is in the neighborhood), we get
Even using this load, we can see from the table that we can expect something like a gain of 60 as long as the emitter bypass capacitor is around 10µF or greater. (Equal impedences for our source and load is our 3dB point, or about two-thirds of our no-load gain.)
At this point, we have a much better idea what the characteristics of this circuit are, and that a more accurate estimate of the frequency of oscillation while using odd part values must remain as stubbornly non-trivial as ever with lots of messy equations. We will just have to accept this fact for now and move on to balancing the circuit stages against one another, considering trade-off possibilities.
We mustn't forget we are working within many different limitations here. The RC's are made the same values in order to simplify the calculations, component procurement, and the possibility of using a triple, ganged potentiometer for the R's so the frequency can be adjusted while keeping them equal (hard to adjust, so better as fixed-frequency.) But if they are the same, each RC stage will be loaded differently, resulting in a different frequency (and phase shifts on each stage), unless each stage is current-buffered. The RC's could be chosen with successively higher impedences for each stage reducing this loading effect, but complicating any precise calculations (first-order estimates remain pretty simple, though). The transistor could be replaced with an operational amplifier, an integrated circuit designed with high gain, high input impedence, low output impedence, and minimal phase shifting, but there are better oscillator configurations if we expand in that direction. This circuit was designed back in the vacuum tube days when circuitry was costly in every sense of the word.
Since our guide for this design appears to be simplicity, a simpler form would do away with the emitter bypass capacitor. (The trade-offs between sections will be a lot more sensitive to changes in values.) Roger Rosenbaum* writes of the no-bypass-capacitor variant: "Since the 4-section network needs a gain of 18.3878, you might try making the Rc of your circuit 11k, and removing the emitter bypass capacitor. This would give the transistor stage a gain of about 20. You could then select Rb and the R of the last section so that their parallel combination was equal to 1332 ohms, and their ratio was such that you got about .5 milliamp of emitter current. This will make the intrinsic emitter resistance about 52 ohms. The base input resistance would then be about beta*552, or about 55,200 ohms (for a beta of 100), which is so high compared to 1332 ohms that it could be neglected. Then the last stage of the phase shift network would be properly loaded."
Let's take circuit simplicity a step further and eliminate one of the RC stages, as well. The circuit becomes even more sensitive since the gain requirement is greater (29 instead of 18) and each RC stage has less "overhead" phase-shift capability to just throw away. The frequency calculation uses the 3-stage RC formula:
The effective output impedence of the unloaded RC stage is the combination of all paths to the supply (or other low-impedence node common to other stages which we will compare it to) which we are treating as part of the output. So we have R (to ground) in parallel with the C paths (complicated, so our first approximation is roughly R) for an output impedence of roughly one-half R. The effective input impedence of an unloaded RC stage at 45° is XC + R, or about 2R. The RC-to-RC loading attenuation of the voltage signal can then be approximated as the ratio of the input impedence of the load to that of the load plus source, or 2/(2+0.5) = 0.8.
* Thanks to Rodger Rosenbaum and the other people at the Usenet group alt.binaries.schematics.electronic who brought this to my attention and who kindly showed me where I went wrong in my phase and frequency calculations.