; adcrdxx.asm
; (c) 2006 by doug garmon
; released under gpl licence

; delay loops removed for this version

portb = $dd01
ddr = $dd03

; cia2 portb data direction register settings
startddr = %00000110
writeddr = %00000111
readddr =  %00000110

start = %00000100
clock = %00000010
writemask = %00000001

; the commands and data in the following section
; are stored in reverse-bit order (backwards)
adccmd = %00000001	; adc read cmd (100)
ctrlrg = %00000110	; control reg setting cmd (011)
chnatt = %00000100	; channel attribute setting cmd (001)
wakeup = %00000010	; channel wakeup cmd (010)

*=$ce00

; jump table 
		jmp read		; read the adc
		jmp init		; perform all the init subroutines
		jmp read		; dummy entry

; return value, general variable (replaces zpage byte)
store		.byte $00

; data section
; bits are stored backwards
; %00000000	channel #0 (000) 3 bits
; %00001000	4-bit control reg setting (0001) 4 bits
; the next two setting could just as easily be reset to effect only chan #0
; %11111111	set all channels for wakeup - 8 bits 
; %11111111	set all channels to analog, not just channel 0 - 8 bits
channel		.byte $00		; channel #
chancrset	.byte %00001000		; channel control reg setting data
chanwake	.byte %11111111		; channel wakeup function -- all
chananalog	.byte %11111111		; set channels to analog -- all 

; read the adc
read		sei			; disable interrupts

		jsr startsig		; the start signal
		
		lda #adccmd		; send adc command
		sta store		; bits to write in store
		ldx #$03
		
sendcmd		jsr sendbits		; send it

		lda channel		; send channel #
		sta store		; bits to write in store
		ldx #$03

sendchan	jsr sendbits		; send it

		lda #readddr		; setup port for read
		sta ddr

		ldx #$04		; two empty clock cycles = 4 clock toggles
cycle		jsr toggleclock	
		dex
		bne cycle

		lda #$00
		sta store		; blank the data store
		
		ldx #$08		; get the 8 bits adc 

; fetch and store the adc bits
; read each data bit in the middle of the clock cycle

readadc		jsr toggleclock
		lda portb		; get adc bit
	
		ror a
		rol store
		
		jsr toggleclock
		dex
		bne readadc		; go back & get next bit

		; NOTE: this (the 9th) bit is shown in only some of the SNAD01C datasheets
		; commented out for now--after some testing this section will be removed...
		
	;	jsr toggleclock		; complete last clock tic...
	;	jsr toggleclock

		cli			; enable interrupts		
		rts
		
; init
; call all the init routines

init

; init the control register settings
;	set the voltage reference to use 'ref' pin

initcrs
		sei
		jsr startsig
		
		lda #ctrlrg		; control reg setting command
		sta store		; bits to write in store
		ldx #$03		; 3 bits
		
		jsr sendbits		; send the cmd
		
		lda chancrset		; cntl reg setting
		sta store
		ldx #$04		; 4 bits in a cr setting
		
		jsr sendbits		; send the setting

; init channels for analog input
initchn
		jsr startsig
		
		lda #chnatt		; channel attribute command
		sta store		; bits to write in store
		ldx #$03		; 3 bits
		
		jsr sendbits		; send the cmd
		
		lda chananalog		; set channels to analog
		sta store
		ldx #$08		; 8 bits
		
		jsr sendbits		; send the setting

; init channels for wakeup function
initwake
		jsr startsig
		
		lda #wakeup		; wakeup command
		sta store		; bits to write in store
		ldx #$03		; 3 bits
		
		jsr sendbits		; send the cmd
		
		lda chanwake		; set channels to wake
		sta store
		ldx #$08		; 8 bits
		
		jsr sendbits		; send the setting
		cli
		
		rts
		
; send bits to adc
; store holds bits (one byte, up to 8 bits)
; x reg holds number of bits

sendbits
		jsr writebit
		jsr toggleclock

		lsr store		; shift the cmd/data bits
		dex
		bne sendbits		; loop back until all bits sent

		rts


; start signal, initiate any transfer
;	startsig also initializes the ddr for whatever cmd follows

startsig
		lda #startddr		; initialize for start
		sta ddr
		lda #start
		sta portb		; begin start signal

		lda #$00
		sta portb		; drop start

		lda #writeddr		; initialize for write
		sta ddr
		rts

; toggles clock

toggleclock
		lda portb
		eor #clock		; eor the current state of clock
		sta portb

		rts

; sets clock, writes to dio
; 	writing only involves two bits (clock and data), so don't set clock and data
; 	separately--just set the two bits as required and write to the port once.

writebit
		lda store
		and #writemask		; and the data bit
		ora #clock		; set the clock bit
		sta portb

		rts